By Jens Eickhoff (auth.), Jens Eickhoff (eds.)
This e-book describes the advance and layout of a distinct mixed information and tool administration infrastructure The use in small satellites offers a few specific standards to the platforms like strength failure robustness and dealing with of other different types of exterior analog and electronic interfaces. those standards result in a practical merge among On Board machine and the satellite's strength keep watch over and Distribution Unit, which leads to a really cutting edge layout or even a patent association. This e-book offers approach engineers and college scholars with the technical wisdom as combine among technical brochure and a person guide.
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Additional resources for A Combined Data and Power Management Infrastructure: For Small Satellites
1 The System Design Concept 7 For taking a spacecraft payload into operation—say ‘‘Spacecraft Equipment 1’’ in Fig. 3—the satellite via its transceiver receives commands from ground which themselves are decoded by the decoder/encoder unit or board and which then are routed as command packets to the OBSW running on the CPU. For payload activation the OBSW first commands the active PCDU controller (A or B) via data bus to supply the payload equipment with power—which means closing the according Latching Current Limiter (LCL) of the—currently active power bus.
38 S. Stratton and D. 1 NVMEM Chip Enable As stated previously, the FM22L16 FRAM devices chosen for the OBC ProcessorBoard have timing that is incompatible with the timing of the LEON3FT. Therefore, certain signals required to control the memory need to be managed by the onboard FPGA. The signals in this instance are the FRAM Chip Enables. The internal logic of the FPGA ensures the proper timing over worst case flight conditions. 2 SRAM Chip Enable The LEON3FT is not designed to interface directly with SRAM devices that implement a stacked die configuration.
Therefore, if a SpaceWire node has data to send it will send 8 bytes of data for each token it receives. The resulting function is simply as follows: As long as each side has data to send, and the data that gets received is taken out of the receive buffer, the system keeps running. For the FLP satellite program, the SBC implements all four of the dedicated SpaceWire ports on the LEON3FT microprocessor operating at 10 Mbs (Fig. 10). 2 The OBC Processor-Boards 37 Fig. 10 LVDS quad driver footprint on SBC layout.